1. Technical Field
The present invention relates to a method and apparatus for testing electrostatic discharge (ESD) devices on a wafer and more particularly to Automated Transmission Line Pulse testing of the ESD devices.
2. Related Art
Transmission Line Pulse (TLP) testing of electrostatic discharge (ESD) devices is performed by using a high-voltage power supply to charge a cable at a voltage level (V), followed by discharging the cable into the ESD device, and then measuring the current (I) through the ESD device. The preceding test may be repeated at successively increasing voltage levels, enabling an I vs. V curve to be generated until the device fails. In that manner, the TLP testing determines a current level at which the ESD device fails. Unfortunately, the aforementioned TLP testing is time consuming and costly.
A system and method is needed for reducing the time and cost of testing ESD devices.
The present invention provides an apparatus for testing a plurality of electrostatic discharge (ESD) devices on a wafer, comprising: a computer system; a pulse generator; a current probe; a switching matrix; an oscilloscope; a ground board; a voltage probe board; and N circuit paths originating from the switching matrix and passing through both the ground board and the voltage probe board,
wherein N is at least 2,
wherein the computer system is electrically coupled to electrical devices including: the pulse generator, the current probe, the switching matrix, the oscilloscope, the ground board, and the voltage probe board,
wherein the computer system, upon execution of a computer code, serves to control and synchronize operation of the electrical devices,
wherein, under program control of the computer system, the pulse generator serves to generate a voltage pulse and to send the voltage pulse to the switching matrix by way of the current probe,
wherein, under program control of the computer system, the current probe serves to detect an electrical current value associated with the voltage pulse and to transmit the electrical current value to the oscilloscope,
wherein, under program control of the computer system, the switching matrix serves to electrically connect Z circuit paths of the N circuit paths to the pulse generator, such that Z is at least 1,
wherein, under program control of the computer system, the ground board serves to electrically disconnect X circuit paths of the Z circuit paths from the pulse generator and to connect the X circuit paths to a ground voltage level,
wherein, under program control of the computer system and if X is less than Z, the voltage probe board serves to detect voltage values in a remaining Z-X circuit paths and to pass the voltage values to the oscilloscope, such that the remaining Z-X circuit paths of the Z circuit paths are not among the X circuit paths, and
wherein the oscilloscope, under program control of the computer system, serves to receive the voltage values and the electrical current value and to pass the voltage values and the electrical current value to computer system.
The present invention provides an electronic structure utilized for enhancing an accuracy of voltage determinations made during testing of a plurality of electrostatic discharge (ESD) devices on a wafer, comprising:
the wafer having M padsets and N conductive pads on each padset, wherein M is at least 1, wherein N is at least 2, and wherein each ESD device is conductively coupled to a unique plurality of pads of a padset of the M padsets;
N circuit paths electrically coupled to the N conductive pads of a first padset of the M padsets; and
an electrical device structure comprising a ground board in series with a voltage probe board, wherein the N circuit paths are electrically coupled to both the ground board and the voltage probe board, and wherein the voltage probe board and the ground board are each positioned no more than about 6 inches from the wafer.
The present invention provides a method for testing a plurality of electrostatic discharge (ESD) devices on a wafer, comprising the steps of:
providing an apparatus comprising: computer system; a pulse generator; a current probe; a switching matrix; an oscilloscope; a ground board; a voltage probe board; and N circuit paths originating from the switching matrix and passing through both the ground board and the voltage probe board, wherein N is at least 2, wherein the computer system is electrically coupled to electrical devices including: the pulse generator, the current probe, the switching matrix, the oscilloscope, the ground board, and the voltage probe board;
controlling and synchronizing, by the computer system upon execution of a computer code, operation of the electrical devices;
generating by the pulse generator, under program control of the computer system, a voltage pulse;
sending by the pulse generator, under program control of the computer system, the voltage pulse to the switching matrix by way of the current probe;
detecting by the current probe, under program control of the computer system, an electrical current value associated with the voltage pulse;
transmitting by the current probe, under program control of the computer system, the electrical current value to the oscilloscope;
electrically connecting by the switching matrix, under program control of the computer system, Z circuit paths of the N circuit paths to the pulse generator, such that Z is at least 1;
electrically disconnecting by the ground board, under program control of the computer system, X circuit paths of the Z circuit paths from the pulse generator;
connecting by the ground board, under program control of the computer system, the X circuit paths to a ground voltage level;
if X is less than Z, detecting voltage values by the voltage probe board, under program control of the computer system, a remaining Z-X circuit paths, such that the remaining Z-X circuit paths of the Z circuit paths are not among the X circuit paths;
passing by the voltage probe board, under program control of the computer system, the voltage values to the oscilloscope;
receiving by the oscilloscope, under program control of the computer system, the voltage values and the electrical current value; and
passing by the oscilloscope, under program control of the computer system, the voltage values and the electrical current value to computer system.
The present invention provides a method for testing a plurality of electrostatic discharge (ESD) devices on a wafer, comprising the steps of:
providing the wafer having M padsets and N conductive pads on each padset, wherein M is at least 1, wherein N is at least 2, and wherein each ESD device is conductively coupled to a unique plurality of pads of a padset of the M padsets;
providing a computer system;
denoting the plurality of ESD devices as E1, E2, . . . , E1, wherein I denotes the number of said ESD devices;
sequencing, under program control of the computer system, the testing of the ESD devices E1, E2, . . . E1, wherein the testing of each ESD device of the ESD devices E1, E2, E1 is under program control of the computer system.
The present invention provides a method for enhancing an accuracy of voltage determinations made during testing of a plurality of electrostatic discharge (ESD) devices on a wafer, comprising the steps of:
providing the wafer having M padsets and N conductive pads on each padset, wherein M is at least 1, wherein N is at least 2 and wherein each ESD device is conductively coupled to a unique plurality of pads of a padset of the M padsets;
providing N circuit paths electrically coupled to the N conductive pads of a first padset of the M padsets;
providing an electrical device structure comprising a ground board in series with a voltage probe board;
positioning the voltage probe board and the ground board such that the voltage probe board and the ground board are each positioned no more than about 6 inches from the wafer; and
electrically coupling the N circuit paths to both the ground board and the voltage probe board.
The present invention provides a computer system for testing a plurality of electrostatic discharge (ESD) devices on a wafer, comprising:
a processor;
an input device coupled to the processor;
an output device coupled to the processor;
a first memory device coupled to the processor;
a computer code stored in the first memory device, wherein the processor executes the computer code, wherein the computer code comprises an algorithm which controls the testing of the plurality of ESD devices in the wafer, and wherein the algorithm implements an Automated Transmission Line Pulse (ATLP) testing of the ESD devices.
The present invention provides a computer program product, comprising: a computer usable medium having a computer readable program code embodied therein for testing a plurality of electrostatic discharge (ESD) devices on a wafer, wherein the computer readable program code includes an algorithm for implementing the testing by the Automated Transmission Line Pulse (ATLP) testing method.
The present invention provides a system and method which reduces the time and cost of testing ESD devices.